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| Ordering number : EN*5041A CMOS LSI LC11011-141 Computer Image Signal Processing Full-Color Gray-Scale Processor Preliminaly Overview The LC11011-141 is a pseudo gray scale processor for TFT LCD. It allows LCD panels with inputs of three to six bits per RGB to display the equivalent of 16.7 million colors. Package Dimensions unit: mm 3151-QFP100E [LC11011-141] Features * Handles 8-bits of input data (256-scale data) for each of the RGB colors. * Operating mode selection of three, four, or six bit driver outputs * Realizes reduced resolution loss (as compared to dithering techniques) by using intra- and inter-frame error diffusion processing. * Supports both 5 V and low voltage (3.3 V) operation. * Operates with arbitrary clock frequencies up to 50 MHz (at 5 V) or up to 30 MHz (at 3.3 V). * Can operate independently of the number of displayed pixels since internal operation is controlled by the horizontal and vertical synchronization signals. SANYO: QFP100E Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Input and output voltages Operating temperature Storage temperature Symbol VDD max VI, VO Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 0 to +70 -40 to +125 Unit V V C C Electrical Characteristics: At an operating voltage of 5.0 V Operating Ranges at Ta = 0 to +70C Ratings Parameter Supply voltage Input voltage Clock frequency Symbol VDD VIN fclk Conditions min 4.5 0 typ 5.0 max 5.5 VDD 50 Unit V V MHz SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22896HA (OT)/No. 5041-1/7 LC11011-141 DC Characteristics at Ta = 0 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V Ratings Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Symbol VIH VIL VOH VOL CMOS level CMOS level IOH (-4 mA) IOL (4 mA) 40 2.4 0.4 70 Conditions min 0.7 VDD 0.3 VDD typ max Unit V V V V mA Supply current ICC * Note: * The test conditions are: fCP = 25.175 MHz, VDD = 5.0 V, CL = 15 pF (measured with VGA timing) Switching Characteristics at Ta = 0 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V, CL = 15 pF Ratings Parameter Dot clock cycle time Hsync low level pulse width Vsync low level pulse width Data setup time Data hold time Control signal setup time Control signal hold time CLK propagation delay time CLK propagation delay time CLKB propagation delay time CLKB propagation delay time Control signal propagation delay time Data output propagation delay time Symbol Tdclk Thpw Tvpw Tdsu Tdhd Tcsu Tchd Ttdhh Ttdll Ttdhl Ttdlh Ttctl Ttdata Conditions min 20 2 Tdclk 2 Tdclk 5 5 5 5 2 2 2 2 2 Tdclk + 3 2 Tdclk + 3 3 4 4 4 2 Tdclk + 6 2 Tdclk + 6 6 7 7 7 2 Tdclk + 10 2 Tdclk + 11 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Electrical Characteristics: At an operating voltage of 3.3 V Operating Ranges at Ta = 0 to +70C Ratings Parameter Supply voltage Input voltage Clock frequency Symbol VDD VIN fclk Conditions min 3.0 0 typ 3.3 max 3.6 VDD 30 Unit V V MHz DC Characteristics at Ta = 0 to +70C, VSS = 0 V, VDD = 3.0 to 3.6 V Ratings Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Symbol VIH VIL VOH VOL CMOS level CMOS level IOH (-2 mA) IOL (2 mA) 30 2.2 0.4 45 Conditions min 0.7 VDD 0.3 VDD typ max Unit V V V V mA Supply current ICC * Note: * The test conditions are: fclk = 25.175 MHz, VDD = 3.3 V, CL = 15 pF (measured with VGA timing) No. 5041-2/7 LC11011-141 Switching Characteristics at Ta = 0 to +70C, VSS = 0 V, VDD = 3.0 to 3.6 V, CL = 15 pF Ratings Parameter Dot clock cycle time Hsync low level pulse width Vsync low level pulse width Data setup time Data hold time Control signal setup time Control signal hold time CLK propagation delay time CLK propagation delay time CLKB propagation delay time CLKB propagation delay time Control signal propagation delay time Data output propagation delay time Symbol Tdclk Thpw Tvpw Tdsu Tdhd Tcsu Tchd Ttdhh Ttdll Ttdhl Ttdlh Ttctl Ttdata Conditions min 33 2 Tdclk 2 Tdclk 10 10 10 10 2 2 2 2 2 Tdclk + 5 2 Tdclk + 5 5 6 6 6 2 Tdclk + 10 2 Tdclk + 10 12 14 14 14 2 Tdclk + 22 2 Tdclk + 24 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Pin Assignment No. 5041-3/7 LC11011-141 Block Diagram No. 5041-4/7 LC11011-141 Pin Functions Symbol VDD Pin No. 5, 21, 28, 32, 41, 61, 68, 91 10, 15, 20, 26, 30, 34, 35, 40, 46,51, 56, 66, 71, 73, 82, 87, 90, 98 24, 76, 77 I/O Input Power supply (+5 V) Function VSS NC Input GND (0 V) -- Must be left open. Mode selection signals [0:3] for the gray scale mode. The setting process for the mode selection lines is described below. MODESEL0 is the LSB, and MODESEL3 is the MSB. Note that modes 8, 9, C, D and E are compatible with the LC1001-131 (a product that handles 6-bits of input for each of the RGB signals). Color scale mode MODESEL0 MODESEL1 MODESEL2 MODESEL3 0 L L L L Intra-frame processing Inter-frame processing Y Y 8 3 1 H L L L Y R Y 8 4 Y 8 6 2 L H L L 3 H H L L Y R N 8 4 N 8 5 N 8 6 Y 6 3 Y 6 4 4 L L H L 5 H L H L Y 6 L H H L Y 7 H H H L Y 8 L L L H Y 9 H L L H Y R R N 6 3 N 6 4 N 6 5 A L H L H B H H L H C L L H H Y D H L H H Y E L H H H Y R F H H H H MODESEL0 1 Input MODESEL1 2 Input Processing Number of valid input bits Number of output bits MODESEL2 3 Input Note: Y = yes, N = no, R = reserved Gray scale modes 0, 8 and C Gray scale modes 1 and 9 Gray scale mode 3 Gray scale modes 5 and D Operating mode for TFT-LCD modules using 3-bit source drivers. Operating mode for TFT-LCD modules using 4-bit source drivers. Operating mode for TFT-LCD modules using 6-bit source drivers. Operating mode for TFT-LCD modules that perform FRC or other inter-frame processing. Operating mode for TFT-LCD modules that perform FRC or other inter-frame processing. MODESEL3 4 Input Gray scale modes 6, 7 and E Note: Do not use gray scale modes 0, 1, 3, 8 and 9 with LCD modules that perform FRC or other interframe processing. Input bypass pin. When this pin is low, the LC11011-141 performs no gray scale processing, but rather simply passes the input signals through unchanged. When a low level input on this pin is sampled on the rising edge of the clock, the IC will begin the output of unchanged data two clock cycles later. BYPASS TEST0 TEST1 TEST2 TEST3 SCLK SRDATA [0:7] SGDATA [0:7] SBDATA [0:7] Shsync Svsync SHDEN SCTL0 SCTL1 CLKSEL CLK CLKB 100 6 7 8 9 67 57 to 60, 62 to 65 78 to 81, 83 to 86 88, 89, 92 to 97 69 70 72 74 75 99 31 33 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Test pins [0:3]; left open in normal operation. Display dot clock input. Data is processed according to this clock signal. Input pins for red, green and blue scale data. SRDATA7, SGDATA7, and SBDATA7 are the MSBs. SRDATA0, SGDATA0, and SBDATA0 are the LSBs. Horizontal and vertical synchronization signal inputs. These are the sources for the Hsync and Vsync signals. These are also used to control data processing. These are low level active signals. Horizontal data valid period signal input. Set this pin high during periods when the horizontal data is valid. If this signal is not used, tie it high, and set the input data to zero during the horizontal blanking period. LCD control inputs. Input control signals that must be matched to the data signal timing. These are the sources for the CTL signals. If the CTL [0:1] signals are not used, there is no need to input the SCTL [0:1] signals. CLKSEL is the dot clock output selection. It is used to select the output mode of the dot clock signal output pin. If CLKSEL is low: A signal with the same phase as the SCLK pin is output from the CLK pin. If CLKSEL is high: A signal with the opposite phase from the SCLK pin is output from the CLKB pin. Continued on next page. No. 5041-5/7 LC11011-141 Continued from preceding page. Symbol RDATA [0:7] Pin No. 11 to 14, 16 to 19 I/O Output Function Red, green and blue gray scale data output pins. These are delayed by 2 clock cycles with respect to the input data. RDATA7, GDATA7 and BDATA7 are the MSBs. In modes 0, 8, C and F, RDATA5, GDATA5 and BDATA5 are the LSBs. In these modes, RDATA [0:4], GDATA [0:4] and BDATA [0:4] are not used. In modes 1, 5, 9 and D, RDATA4, GDATA4 and BDATA4 are the LSBs. In these modes, RDATA [0:3], GDATA [0:3] and BDATA [0:3] are not used. In modes 6 and E, RDATA3, GDATA3 and BDATA3 are the LSBs. In these modes, RDATA [0:2], GDATA [0:2] and BDATA [0:2] are not used. In modes 3 and 7, RDATA2, GDATA2 and BDATA2 are the LSBs. In these modes, RDATA [0:1], GDATA [0:1] and BDATA [0:1] are not used. Horizontal and vertical synchronization signal outputs. To match the data signal timing these are delayed by two clock cycles with respect to their input signals. Horizontal data valid period signal output LCD control signal outputs. To match the data signal timing these are delayed by two clock cycles with respect to the SCTL [0:1] input signals. GDATA [0:7] 36 to 39, 42 to 45 Output BDATA [0:7] Vsync Hsync HDEN CLT0 CLT1 47 to 50, 52 to 55 27 29 25 22 23 Output Output Output Output Output Output Timing Chart No. 5041-6/7 LC11011-141 Continued from preceding page. Usage Note Since this LSI performs spatial modulation using an error diffusion algorithm, patterns that differ from the original images may be displayed for certain display pattern and gray-scale mode combinations. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5041-7/7 |
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